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Power integrityPDNFundamentals

Why bypass networks top out, and what lies beyond 100 dB

Capacitors resonate, ferrite beads saturate and LDO rejection rolls off. This is the physics behind the 80–90 dB ceiling of conventional PDN filtering, and what happens when one part removes it.

The usual recipe

Most boards filter a noisy rail the same way. There is a bulk capacitor, a spread of MLCCs (10 µF, 1 µF, 100 nF, 10 nF), a ferrite bead in series, and often an LDO post-regulator for the sensitive loads. Each part covers one slice of the spectrum, and every slice has an edge. In our characterization, even a well-designed network of this kind reaches about 80 to 90 dB of rejection at best, and it fades out somewhere around 300 to 400 MHz.

Four effects set that ceiling.

1. Capacitors stop being capacitors

Every real capacitor has an equivalent series inductance (ESL). Above its self-resonant frequency its impedance rises with frequency, as an inductor’s would:

fSRF = 1 / (2π √(ESL × C))

Take a 100 nF part with 0.5 nH of mounted inductance. It resonates near 22.5 MHz. A 1 nF part with the same mounting resonates near 225 MHz. On a real board, the pad and via inductance often exceeds the capacitor’s own ESL. That is why MLCC decoupling runs out of effect in the hundreds of megahertz, however many capacitors you add. Mixing values to cover more bands creates anti-resonance peaks between neighbouring self-resonances, where the combined impedance spikes rather than dips.

2. Ferrite beads change with current

A ferrite bead’s impedance depends on its DC bias. In Ferrite Beads Demystified, ADI’s Jefferson Eco and Aldrick Limjoco show that a bead’s inductance falls substantially as load current rises. They suggest running a bead at about 20% of its rated current to keep its filtering.

A bead combined with decoupling capacitors also forms an LC low-pass filter. If it is undamped, that filter can peak by roughly 10 to 15 dB at resonance. If the peak lands near a switching frequency, the filter amplifies exactly the noise it was meant to remove.

3. LDO rejection rolls off

An LDO’s power-supply rejection ratio is high at low frequency and falls as frequency rises. TI’s LDO Basics makes the practical point: a PSRR figure at 120 Hz or 1 kHz tells you nothing about the ripple at a switcher’s fundamental. You need the PSRR curve at the ripple frequency itself. At higher frequencies, the output capacitor and its parasitics dominate the result. The LDO also adds noise of its own, including a 1/f region that sets a floor below which it cannot clean a rail.

4. The board is part of the filter

Plane resonances, via inductance and return paths all become part of the filter at gigahertz frequencies. No part placed on a pad can be better than the loop it sits in.

Why the ceiling matters more every year

  • Timing. Power supply induced jitter (PSIJ) is the point where power integrity becomes signal integrity. Ripple on a supply changes CMOS gate delay, and that turns voltage noise directly into jitter on clock and data edges. A DesignCon 2018 paper on chip-level power integrity for high-speed serial links, by Shayan Shahramian and colleagues at Huawei Canada and the University of Toronto, treats this coupling as a first-order design problem.
  • Phase noise. An oscillator’s frequency shifts slightly with its supply voltage. Supply noise therefore becomes phase-noise sidebands and spurs.
  • SNR. In ADC and sensor front ends, supply noise lands in the signal band and reduces resolution.
  • Headroom. As process nodes shrink, operating voltages fall while multi-rail SoCs, SSDs and DDR keep adding rails. A fixed amount of noise takes a larger bite of a smaller margin.

Decibels as voltage ratios

Rejection figures are easier to judge as voltage ratios.

Rejection Voltage ratio 100 mV of noise becomes
40 dB 100× 1 mV
80 dB 10,000× 10 µV
100 dB 100,000× 1 µV
120 dB 1,000,000× 100 nV
140 dB 10,000,000× 10 nV
160 dB 100,000,000× 1 nV

Moving from 80 dB to 120 dB is not a 50% improvement. It is 100 times less residual noise, and every further 20 dB divides what is left by 10 again.

What Harmony does differently

The Harmony PI Filter (TSNJ-5A6L26) is one passive 6-pin part, 2.2 × 2.6 × 0.9 mm. It carries 5 A and draws no power. Its patented SNJ conditioning works in both the time and frequency domains, and its noise suppression reaches from DC up to 20 GHz. It removes the anti-resonance peaks, impedance violations, LC tank oscillations and overshoot that bead-and-capacitor networks cause, and it frees up to 90% of the PDN’s board area by eliminating up to 80% of its passives.

Here is what that adds up to on our bench:

Measure Typical bypass network Harmony PI Filter
Suppression in the critical band 80 to 90 dB, best case About −120 dB with a single Type-B, and −140 to −160 dB with dual Type-B. Both are below most instruments’ floors, so VNA traces read about −100 dB from 2 MHz to 500 MHz.
Effective bandwidth Up to about 300 to 400 MHz DC to 6 GHz (Type-B). 62 dB at 10 GHz and 51 dB at 20 GHz (dual Type-B).
PDN shunt impedance Tens to hundreds of milliohms, with resonances 104 to 255 µΩ (Type-B), and 2 to 5 µΩ from 14 to 300 MHz (dual Type-B)
Parts for a 6 GHz filter 15 in TI’s LP877451Q1EVM broadband filter 3
Ultra-low-noise LDO output The LDO’s own 1/f noise floor A further 20 dB lower (ADM7150 in a defense radio)
Switching regulator ripple 10 mVp-p on an ADI LT8622S Silent Switcher 4.48 µVp-p

The native S21 of the part alone is lower, about 87 dB at its deepest near 13 MHz, because it is measured without bulk capacitance. Add two 47 µF capacitors at VOUT and you have the Type-B configuration, which nearly every application figure above uses.

A checklist for a Harmony-based PDN

  1. Choose the location for the noise you are fighting. For SNJ in a switcher’s loop, put it near the power inductor and the feedback node. For a rail that travels and picks up radiated energy, put it at the point of load. To isolate noise-generating subsystems from noise-sensitive ones, put it between them.
  2. Use the Type-B circuit. Put two 47 µF, 10 V capacitors at VOUT. Small-value capacitors are not needed.
  3. Ground it well. Put a ground plane immediately below the part and vias right at each GND terminal. Do not use thermal reliefs. Use via-in-pad, and stitch ground layers with closely spaced vias.
  4. Respect the ratings. The part is rated for 6 V DC and for 5 A at 25 °C, so derate for temperature and airflow.
  5. Measure with enough bandwidth. If your instrument stops at 20 MHz, you will never see the difference.

Sources

  1. J. Eco and A. Limjoco, "Ferrite Beads Demystified," Analog Dialogue 50-02, February 2016
  2. A. Paxton, "LDO Basics: Power Supply Rejection Ratio," Texas Instruments
  3. Toshiba, "Simple Guide to Improving Ripple Rejection Ratio of LDO Regulators"
  4. PSIJ: How power supply noise becomes jitter (SIPI)
  5. Shayan Shahramian et al. (Huawei Canada and University of Toronto), "Chip-level Power Integrity Methodology for High-Speed Serial Links," DesignCon 2018
  6. TransSiP, Harmony PI Filter datasheet TSNJ-DS-R009, Rev 9
  7. E. Bogatin, L. Smith and S. Sandler, "The Myth of Three Capacitor Values," Signal Integrity Journal